From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
The dbuf state will be where we collect all the inter-pipe dbuf
allocation stuff. Start by moving the actual per-pipe ddb entries
there.
v2: Rebase
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++++++--------
.../drm/i915/display/intel_display_types.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 16 ++++-------
drivers/gpu/drm/i915/intel_pm.h | 4 +++
4 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a185b9e25cc3..9c6b9cebe8b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15303,6 +15303,10 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
struct intel_crtc *crtc;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
@@ -15317,7 +15321,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
/* ignore allocations for crtc's that have been turned off. */
if (!needs_modeset(new_crtc_state)) {
- entries[pipe] = old_crtc_state->wm.skl.ddb;
+ entries[pipe] = old_dbuf_state->ddb[pipe];
update_pipes |= BIT(pipe);
} else {
modeset_pipes |= BIT(pipe);
@@ -15341,11 +15345,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if ((update_pipes & BIT(pipe)) == 0)
continue;
- if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
+ if (skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe],
entries, I915_MAX_PIPES, pipe))
continue;
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_dbuf_state->ddb[pipe];
update_pipes &= ~BIT(pipe);
intel_update_crtc(crtc, state, old_crtc_state,
@@ -15357,8 +15361,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
* then we need to wait for a vblank to pass for the
* new ddb allocation to take effect.
*/
- if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
- &old_crtc_state->wm.skl.ddb) &&
+ if (!skl_ddb_entry_equal(&new_dbuf_state->ddb[pipe],
+ &old_dbuf_state->ddb[pipe]) &&
(update_pipes | modeset_pipes))
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -15379,10 +15383,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
is_trans_port_sync_slave(new_crtc_state))
continue;
- drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
- entries, I915_MAX_PIPES, pipe));
+ drm_WARN_ON(&dev_priv->drm,
+ skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe],
+ entries, I915_MAX_PIPES, pipe));
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_dbuf_state->ddb[pipe];
modeset_pipes &= ~BIT(pipe);
if (is_trans_port_sync_mode(new_crtc_state)) {
@@ -15414,10 +15419,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if ((modeset_pipes & BIT(pipe)) == 0)
continue;
- drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
- entries, I915_MAX_PIPES, pipe));
+ drm_WARN_ON(&dev_priv->drm,
+ skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe],
+ entries, I915_MAX_PIPES, pipe));
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_dbuf_state->ddb[pipe];
modeset_pipes &= ~BIT(pipe);
intel_update_crtc(crtc, state, old_crtc_state, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b51aef2ec770..e35aae029cd4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -703,7 +703,6 @@ struct intel_crtc_wm_state {
struct {
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
- struct skl_ddb_entry ddb;
struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
} skl;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 94847225c84f..b33d99a30116 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3911,16 +3911,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
* grab _all_ crtc locks, including the one we currently hold.
*/
if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes &&
- !dev_priv->wm.distrust_bios_wm) {
- /*
- * alloc may be cleared by clear_intel_crtc_state,
- * copy from old state to be sure
- *
- * FIXME get rid of this mess
- */
- *alloc = to_intel_crtc_state(for_crtc->base.state)->wm.skl.ddb;
+ !dev_priv->wm.distrust_bios_wm)
return 0;
- }
/*
* Get allowed DBuf slices for correspondent pipe and platform.
@@ -4528,7 +4520,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(crtc_state->uapi.state);
+ struct intel_dbuf_state *dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+ struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
u16 alloc_size, start = 0;
u16 total[I915_MAX_PLANES] = {};
u16 uv_total[I915_MAX_PLANES] = {};
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 8204d6a5526c..d9f84d93280d 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,8 +8,10 @@
#include <linux/types.h>
+#include "display/intel_display.h"
#include "display/intel_global_state.h"
+#include "i915_drv.h"
#include "i915_reg.h"
struct drm_device;
@@ -63,6 +65,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
struct intel_dbuf_state {
struct intel_global_state base;
+ struct skl_ddb_entry ddb[I915_MAX_PIPES];
+
u8 enabled_slices;
u8 active_pipes;
};
--
2.24.1
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