For Gen11+ platforms BSpec suggests disabling specific QGV points separately, depending on bandwidth limitations and current display configuration. Thus it required adding a new PCode request for disabling QGV points and some refactoring of already existing SAGV code. Also had to refactor intel_can_enable_sagv function, as current seems to be outdated and using skl specific workarounds, also not following BSpec for Gen11+. v17: Had to rebase the whole series. v18: Resent whole series as new patch was introduced. Stanislav Lisovskiy (8): drm/i915: Start passing latency as parameter drm/i915: Introduce skl_plane_wm_level accessor. drm/i915: Add intel_bw_get_*_state helpers drm/i915: Introduce more *_state_changed indicators drm/i915: Refactor intel_can_enable_sagv drm/i915: Added required new PCode commands drm/i915: Restrict qgv points which don't have enough bandwidth. drm/i915: Enable SAGV support for Gen12 drivers/gpu/drm/i915/display/intel_atomic.c | 2 + drivers/gpu/drm/i915/display/intel_bw.c | 211 +++++-- drivers/gpu/drm/i915/display/intel_bw.h | 36 ++ drivers/gpu/drm/i915/display/intel_display.c | 141 ++++- .../drm/i915/display/intel_display_types.h | 34 +- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_pm.c | 581 +++++++++++++++--- drivers/gpu/drm/i915/intel_pm.h | 4 +- drivers/gpu/drm/i915/intel_sideband.c | 2 + 10 files changed, 864 insertions(+), 154 deletions(-) -- 2.24.1.485.gad05a3d8e5 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
