On Wed, 2020-02-19 at 13:56 -0800, Matt Roper wrote:
> We need to explicitly set the TLB Request Timer initial value in the
> BW_BUDDY registers to 0x8 rather than relying on the hardware
> default.
>
> v2: Apply missing REG_FIELD_PREP to ensure 0x8 is placed in the
> correct
> bits during the rmw. (Jose)
>
> Bspec: 52890
> Bspec: 50044
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0d94fe01be7f..8ba68ec6dc24 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5003,6 +5003,14 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
> table[i].page_mask);
> intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> table[i].page_mask);
> +
> + /* Wa_22010178259:tgl */
> + intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> + BW_BUDDY_TLB_REQ_TIMER_MASK,
> + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK
> , 0x8));
> + intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> + BW_BUDDY_TLB_REQ_TIMER_MASK,
> + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK
> , 0x8));
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index a6847f26678c..d829b9ae8402 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7766,6 +7766,7 @@ enum {
> #define BW_BUDDY1_CTL _MMIO(0x45140)
> #define BW_BUDDY2_CTL _MMIO(0x45150)
> #define BW_BUDDY_DISABLE REG_BIT(31)
> +#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
>
> #define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)
> #define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)
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