On Thu, Feb 13, 2020 at 03:47:59PM +0000, Chris Wilson wrote:
> Cryptic notes in bspec say that "The MBC Driver Boot Enable bit in MBCTL
> register must be set before this register is written to upon boot up
> (including S3 exit)."
>
> We tried adding it to our list of verified workarounds, but our
> self checks spot that the bit does not stick. It's only meant to be
> cleared after a FLR. As it fails our verification, just blindly apply
> the bit prior to loading the ppGTT.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index f70b903a98bc..e41a329d435a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -642,6 +642,9 @@ static void set_pp_dir(struct intel_engine_cs *engine)
> if (vm) {
> struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>
> + intel_uncore_rmw(engine->uncore, GEN6_MBCTL,
> + 0, GEN6_MBCTL_ENABLE_BOOT_FETCH)
Wasn't setting this bit implicated in some regressions long ago?
> +
> ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
> ENGINE_WRITE(engine, RING_PP_DIR_BASE,
> px_base(ppgtt->pd)->ggtt_offset << 10);
> --
> 2.25.0
>
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--
Ville Syrjälä
Intel
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