On Wed, 2020-01-29 at 13:42 +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza
> wrote:
> > From: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> >
> > dgfx platforms do not support CPU fence and FBC host tracking so
> > lets avoid write to removed registers.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx
> > >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f0d24a1dec1..12900b8ce28e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct
> > drm_i915_private *dev_priv)
> > break;
> > }
> >
> > - if (params->fence_id >= 0) {
> > + if (IS_DGFX(dev_priv)) {
> > + /*
> > + * dGFX GPUs don't have apperture or fences and only
> > rely on FBC
> > + * render nuke to track frontbuffer modifications
> > + */
> > + } else if (params->fence_id >= 0) {
> > dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
> > intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
> > SNB_CPU_FENCE_ENABLE | params-
> > >fence_id);
>
> if (fence) {
> do stuff
> } else if (num_fences) {
> do other stuff
> }
Did not get what you want here.
It is covering all cases:
- DGFX that don't have the registers
- Setting the registers when fence_id >= 0
- Clearing the register when fences_id == -1
>
> > --
> > 2.25.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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