Reducing audience as this series is of high interest externally. I fully agree with Joonas' suggestion here, and we have been looking at doing just that. But can we iterate as a follow up patch series? Putting in the infra to support igt assembly from source will take a little time (igt assembler doesn't like the source right now, so it looks like it will need updating), and we are under pressure to get this security fix out. Jon > -----Original Message----- > From: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > Sent: Friday, January 31, 2020 1:52 AM > To: Abodunrin, Akeem G <akeem.g.abodunrin@xxxxxxxxx>; Wilson, Chris P > <chris.p.wilson@xxxxxxxxx>; Phillips, D Scott <d.scott.phillips@xxxxxxxxx>; > Vetter, Daniel <daniel.vetter@xxxxxxxxx>; Stewart, David C > <david.c.stewart@xxxxxxxxx>; dri-devel@xxxxxxxxxxxxxxxxxxxxx; Balestrieri, > Francesco <francesco.balestrieri@xxxxxxxxx>; intel-gfx@xxxxxxxxxxxxxxxxxxxxx; > Nikula, Jani <jani.nikula@xxxxxxxxx>; Bloomfield, Jon > <jon.bloomfield@xxxxxxxxx>; Kuoppala, Mika <mika.kuoppala@xxxxxxxxx>; > Aran, Omer <omer.aran@xxxxxxxxx>; Pathi, Pragyansri > <pragyansri.pathi@xxxxxxxxx>; Kumar Valsan, Prathap > <prathap.kumar.valsan@xxxxxxxxx>; Dutt, Sudeep <sudeep.dutt@xxxxxxxxx>; > Luck, Tony <tony.luck@xxxxxxxxx> > Subject: Re: [PATCH 2/2] drm/i915/gen7: Clear all EU/L3 residual contexts > > Quoting Akeem G Abodunrin (2020-01-30 18:57:21) > > From: Prathap Kumar Valsan <prathap.kumar.valsan@xxxxxxxxx> > > > > On gen7 and gen7.5 devices, there could be leftover data residuals in > > EU/L3 from the retiring context. This patch introduces workaround to clear > > that residual contexts, by submitting a batch buffer with dedicated HW > > context to the GPU with ring allocation for each context switching. > > > > This security mitigation change does not trigger any performance > > regression. Performance is on par with current mainline/drm-tip. > > > > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > > Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@xxxxxxxxx> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@xxxxxxxxx> > > Cc: Chris Wilson <chris.p.wilson@xxxxxxxxx> > > Cc: Balestrieri Francesco <francesco.balestrieri@xxxxxxxxx> > > Cc: Bloomfield Jon <jon.bloomfield@xxxxxxxxx> > > Cc: Dutt Sudeep <sudeep.dutt@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/gt/gen7_renderclear.c | 535 ++++++++++++++++++ > > drivers/gpu/drm/i915/gt/gen7_renderclear.h | 15 + > > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 17 +- > > .../gpu/drm/i915/gt/intel_ring_submission.c | 3 +- > > drivers/gpu/drm/i915/i915_utils.h | 5 + > > 6 files changed, 572 insertions(+), 4 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/gt/gen7_renderclear.c > > create mode 100644 drivers/gpu/drm/i915/gt/gen7_renderclear.h > > > > diff --git a/drivers/gpu/drm/i915/Makefile > b/drivers/gpu/drm/i915/Makefile > > index 3c88d7d8c764..f96bae664a03 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -78,6 +78,7 @@ gt-y += \ > > gt/debugfs_gt.o \ > > gt/debugfs_gt_pm.o \ > > gt/gen6_ppgtt.o \ > > + gt/gen7_renderclear.o \ > > gt/gen8_ppgtt.o \ > > gt/intel_breadcrumbs.o \ > > gt/intel_context.o \ > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > > new file mode 100644 > > index 000000000000..a6f5f1602e33 > > --- /dev/null > > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > > @@ -0,0 +1,535 @@ > > +// SPDX-License-Identifier: MIT > > +/* > > + * Copyright © 2019 Intel Corporation > > + */ > > + > > +#include "gen7_renderclear.h" > > +#include "i915_drv.h" > > +#include "i915_utils.h" > > +#include "intel_gpu_commands.h" > > + > > +#define MAX_URB_ENTRIES 64 > > +#define STATE_SIZE (4 * 1024) > > +#define GT3_INLINE_DATA_DELAYS 0x1E00 > > +#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) > > + > > +/* > > + * Media CB Kernel for gen7 devices > > + * TODO: Add comments to kernel, indicating what each array of hex does > or > > + * include header file, which has assembly source and support in igt to be > > + * able to generate kernel in this same format > > + */ > > Having the original source code for the kernels in IGT is the > best way to proceed. The kernels should also be split into > separate files which can be generated from IGT and copied > over as-is for easy verification. > > Regards, Joonas _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
