On Mon, Oct 29, 2012 at 07:26:42PM +0200, Jani Nikula wrote:
> Mask the value, not the register. Spotted while reading the code.
>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
>
> ---
>
> Only compile tested. Is there a bug that might match this?
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a5be346..6f8cf2a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2804,8 +2804,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
> if (HAS_PCH_IBX(dev)) {
> I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
> I915_WRITE(FDI_RX_CHICKEN(pipe),
> - I915_READ(FDI_RX_CHICKEN(pipe) &
> - ~FDI_RX_PHASE_SYNC_POINTER_EN));
> + I915_READ(FDI_RX_CHICKEN(pipe)) &
> + ~FDI_RX_PHASE_SYNC_POINTER_EN);
On second look, we write the same register in the previous line, and the
w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the logic,
then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle
~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder. So
the right things seems to be to simply kill the 2nd write.
-Daniel
> } else if (HAS_PCH_CPT(dev)) {
> cpt_phase_pointer_disable(dev, pipe);
> }
> --
> 1.7.9.5
>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
