Looks good to me.
On 2020-01-16 at 10:54:19 -0800, José Roberto de Souza wrote:
> This will calculaet the DC3CO exit delay only once per full modeset.
>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Anshuman Gupta <anshuman.gupta@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
Reviewed-by: Anshuman Gupta <anshuman.gupta@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1d2fd1a8925a..e64e0c4c80dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -802,7 +802,9 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> dev_priv->psr.busy_frontbuffer_bits = 0;
> dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> - dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state);
> + /* DC5/DC6 required idle frames = 6 */
> + val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> + dev_priv->psr.dc3co_exit_delay = val;
> dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
>
> /*
> @@ -1277,8 +1279,6 @@ static void
> tgl_dc3co_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits, enum fb_op_origin origin)
> {
> - u32 delay;
> -
> mutex_lock(&dev_priv->psr.lock);
>
> if (!dev_priv->psr.dc3co_enabled)
> @@ -1296,10 +1296,8 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
> goto unlock;
>
> tgl_psr2_enable_dc3co(dev_priv);
> - /* DC5/DC6 required idle frames = 6 */
> - delay = 6 * dev_priv->psr.dc3co_exit_delay;
> mod_delayed_work(system_wq, &dev_priv->psr.idle_work,
> - usecs_to_jiffies(delay));
> + dev_priv->psr.dc3co_exit_delay);
>
> unlock:
> mutex_unlock(&dev_priv->psr.lock);
> --
> 2.25.0
>
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