On Fri, Jan 10, 2020 at 12:05:47AM +0200, Stanislav Lisovskiy wrote: > There seems to be some undocumented bandwidth > bottleneck/dependency which scales with CDCLK, > causing FIFO underruns when CDCLK is too low, > even when it's correct from BSpec point of view. > > Currently for TGL platforms we calculate > min_cdclk initially based on pixel_rate divided > by 2, accounting for also plane requirements, > however in some cases the lowest possible CDCLK > doesn't work and causing the underruns. > We've found experimentally that raising cdclk to > at least pixel_rate (rather than pixel_rate/2) > eliminates these underruns, so let's use this as a > temporary workaround until the hardware team > can suggest a more precise remedy. > > Explicitly stating here that this seems to be currently > rather a Hack, than final solution. > > v2: Use clamp operation instead of min(Matt Roper) > > v3: - Fixed commit message(Matt Roper) > - Now using pixel_rate instead of max_cdclk(Jani Nikula) > - Switched to max from clamp(Ville Syrjälä) > Hopefully this hybrid satisfies everyone :) This seems fine to me. My r-b stands. Matt > > Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/402 > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 7d1ab1e5b7c3..0ce5926006ca 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2004,6 +2004,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > /* Account for additional needs from the planes */ > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); > > + /* > + * HACK. Currently for TGL platforms we calculate > + * min_cdclk initially based on pixel_rate divided > + * by 2, accounting for also plane requirements, > + * however in some cases the lowest possible CDCLK > + * doesn't work and causing the underruns. > + * Explicitly stating here that this seems to be currently > + * rather a Hack, than final solution. > + */ > + if (IS_TIGERLAKE(dev_priv)) > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > + > if (min_cdclk > dev_priv->max_cdclk_freq) { > DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", > min_cdclk, dev_priv->max_cdclk_freq); > -- > 2.24.1.485.gad05a3d8e5 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
