On Tue, Dec 31, 2019 at 12:27:08PM +0000, Chris Wilson wrote:
> The coarse power gating was disabled as part of commit 2248a28384fe
> ("drm/i915/gen8+: Add RC6 CTX corruption WA") as a prelude to recover
> from the context corruption; the power gating itself has no direct
> impact on the RC6 context corruption. However, that recovery scheme was
> never implemented due to difficult corner cases, and so we no longer need
> to keep the power gating disabled.
>
> Fixes: 2248a28384fe ("drm/i915/gen8+: Add RC6 CTX corruption WA")
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/846
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> Cc: Eero Tamminen <eero.t.tamminen@xxxxxxxxx>
> Cc: Jon Bloomfield <jon.bloomfield@xxxxxxxxx>
Yes, the original reason to disable CPG doesn't apply imo any more:
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b7f122dccdca..85b565e69ad4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1657,8 +1657,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
>
> /* WaRsDisableCoarsePowerGating:skl,cnl */
> -#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> - IS_GEN_RANGE(dev_priv, 9, 10)
> +#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> + (IS_CANNONLAKE(dev_priv) || \
> + IS_SKL_GT3(dev_priv) || \
> + IS_SKL_GT4(dev_priv))
> +
>
> #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
> #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
> --
> 2.25.0.rc0
>
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