Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > Do not reset RING_BB_STATE, leaving it to the default state value. This > prevents bdw/bsw from getting confused when executing batches from the > GGTT. Happily setting up ro registers through ctx image, stamped my me... Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index f0618e6aabd5..2bf6dc6d528d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -3982,7 +3982,6 @@ static void init_common_reg_state(u32 * const regs, > regs[CTX_CONTEXT_CONTROL] = ctl; > > regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID; > - regs[CTX_BB_STATE] = RING_BB_PPGTT; > } > > static void init_wa_bb_reg_state(u32 * const regs, > -- > 2.25.0.rc0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
