On Mon, Dec 23, 2019 at 09:32:40AM -0800, Lucas De Marchi wrote:
> We are currently using a mix of platform name and acronym to name the
> functions. Let's prefer the acronym as it should be clear what platform
> it's about and it's shorter, so it doesn't go over 80 columns in a few
> cases. This converts icelake to icl where appropriate.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Acked-by: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Acked-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 11 +++++------
> drivers/gpu/drm/i915/gt/intel_mocs.c | 6 +++---
> 2 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 98d6bcb4c761..461691cc2f62 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10455,9 +10455,8 @@ static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> }
>
> -static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
> - enum port port,
> - struct intel_crtc_state *pipe_config)
> +static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> + struct intel_crtc_state *pipe_config)
> {
> enum phy phy = intel_port_to_phy(dev_priv, port);
> enum icl_port_dpll_id port_dpll_id;
> @@ -10741,7 +10740,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
> }
>
> if (INTEL_GEN(dev_priv) >= 11)
> - icelake_get_ddi_pll(dev_priv, port, pipe_config);
> + icl_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
> cnl_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_GEN9_BC(dev_priv))
> @@ -10792,7 +10791,7 @@ static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_pr
> return master_select - 1;
> }
>
> -static void icelake_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
> +static void icl_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 transcoders;
> @@ -10948,7 +10947,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>
> if (INTEL_GEN(dev_priv) >= 11 &&
> !transcoder_is_dsi(pipe_config->cpu_transcoder))
> - icelake_get_trans_port_sync_config(pipe_config);
> + icl_get_trans_port_sync_config(pipe_config);
>
> out:
> for_each_power_domain(power_domain, power_domain_mask)
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index cbdeda608359..95f1bc45953b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -267,7 +267,7 @@ static const struct drm_i915_mocs_entry tigerlake_mocs_table[] = {
> L3_3_WB),
> };
>
> -static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
> +static const struct drm_i915_mocs_entry icl_mocs_table[] = {
> /* Base - Uncached (Deprecated) */
> MOCS_ENTRY(I915_MOCS_UNCACHED,
> LE_1_UC | LE_TC_1_LLC,
> @@ -288,8 +288,8 @@ static bool get_mocs_settings(const struct drm_i915_private *i915,
> table->table = tigerlake_mocs_table;
> table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> } else if (IS_GEN(i915, 11)) {
> - table->size = ARRAY_SIZE(icelake_mocs_table);
> - table->table = icelake_mocs_table;
> + table->size = ARRAY_SIZE(icl_mocs_table);
> + table->table = icl_mocs_table;
> table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
> table->size = ARRAY_SIZE(skl_mocs_table);
> --
> 2.24.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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