On Thu, Dec 19, 2019 at 03:33:05PM -0800, Manasi Navare wrote: > While clearing the Ports ync mode enable and master select bits > we need to clear the register completely instead of using disable masks > > v2: > * Just write 0 to the reg (Ville) > * Rebase > > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > Fixes: 51528afe7c5e ("drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence") > Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index c9ba7d7f3787..c484f6df5d87 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3861,7 +3861,6 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_ > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > i915_reg_t reg; > - u32 trans_ddi_func_ctl2_val; > > if (old_crtc_state->master_transcoder == INVALID_TRANSCODER) > return; > @@ -3870,9 +3869,7 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_ > transcoder_name(old_crtc_state->cpu_transcoder)); > > reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder); > - trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE | > - PORT_SYNC_MODE_MASTER_SELECT_MASK); > - I915_WRITE(reg, trans_ddi_func_ctl2_val); > + I915_WRITE(reg, 0); Could probably get rid of 'reg' now too and just I915_WRITE(TRANS_DDI_FUNC_CTL2(...), 0) Up to you. Either way, Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > } > > static void intel_ddi_post_disable(struct intel_encoder *encoder, > -- > 2.19.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
