Hi Chris, > The initial investigated showed that while the PCU on Braswell/Baytrail > controlled RC6 itself. setting the software RC6 request made no > difference. Further testing reveals though that it causes a delay in the > PCU on enabling RC6. > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/763 > Fixes: 730eaeb52426 ("drm/i915/gt: Manual rc6 entry upon parking") > Testcase: igt/perf/rc6-disable > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Andi Shyti <andi.shyti@xxxxxxxxx> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > Cc: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index 4dc82196b285..8ec2b7725141 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -612,6 +612,9 @@ void intel_rc6_park(struct intel_rc6 *rc6) > return; > } > > + if (!(rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE)) > + return; > + Huh? I didn't think this could be necessary! Nice catch! Acked-by: Andi Shyti <andi.shyti@xxxxxxxxx> Thanks, Andi > /* Turn off the HW timers and go directly to rc6 */ > set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE); > set(uncore, GEN6_RC_STATE, 0x4 << RC_SW_TARGET_STATE_SHIFT); > -- > 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
