As Braswell is using aliasing-ppgtt, softpinning is trick as we have to avoid overlapping with HW objects in the GGTT (like context images). Typically allocations are from either end, so if we provide a hint to use the middle, we should be safe from overlap. Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- tests/i915/gem_ctx_engines.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c index 1e82e51ee..55794a438 100644 --- a/tests/i915/gem_ctx_engines.c +++ b/tests/i915/gem_ctx_engines.c @@ -425,7 +425,10 @@ static void independent(int i915) .value = to_user_pointer(&engines), .size = sizeof(engines), }; - struct drm_i915_gem_exec_object2 results = { .handle = gem_create(i915, 4096) }; + struct drm_i915_gem_exec_object2 results = { + .handle = gem_create(i915, 4096), + .offset = gem_aperture_size(i915) / 2, + }; const uint32_t bbe = MI_BATCH_BUFFER_END; int timeline = sw_sync_timeline_create(); uint32_t last, *map; -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx