On 2019-12-05 at 18:05:13 +0530, Animesh Manna wrote:
> As the current usage is restricted to first DSB instance per pipe, so
> existing code could not catch the issue to calculate the mmio offset
> of different DSB instance per pipe. Corrected the offset calculation.
>
> Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
Reviewed-by: Anshuman Gupta <anshuman.gupta@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1a6376a97d48..0b242513e3eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -12076,7 +12076,7 @@ enum skl_power_gate {
> /* This register controls the Display State Buffer (DSB) engines. */
> #define _DSBSL_INSTANCE_BASE 0x70B00
> #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
> - (pipe) * 0x1000 + (id) * 100)
> + (pipe) * 0x1000 + (id) * 0x100)
> #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
> #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
> #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
> --
> 2.22.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
