From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
512B Y tiling is the special case so perhaps makes sense to
flip the flag around and adjust the code accordingly.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +-
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 2 +-
5 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1f1cd7578706..f37c11437cfc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1972,10 +1972,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
/* fall through */
case I915_FORMAT_MOD_Y_TILED:
- if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
- return 128;
- else
+ if (HAS_512_BYTE_Y_TILING(dev_priv))
return 512;
+ else
+ return 128;
case I915_FORMAT_MOD_Yf_TILED_CCS:
if (color_plane == 1)
return 128;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index 1fa592d82af5..e4655366ee00 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -145,7 +145,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
}
if (IS_GEN(i915, 2) ||
- (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
+ (tiling == I915_TILING_Y && !HAS_512_BYTE_Y_TILING(i915)))
tile_width = 128;
else
tile_width = 512;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 6ce9167f8c9f..ccd4a4c3f6dc 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -276,7 +276,7 @@ setup_tile_size(struct tile *tile, struct drm_i915_private *i915)
tile->width = 128;
tile->size = 11;
} else if (tile->tiling == I915_TILING_Y &&
- HAS_128_BYTE_Y_TILING(i915)) {
+ !HAS_512_BYTE_Y_TILING(i915)) {
tile->height = 32;
tile->width = 128;
tile->size = 12;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14744c114475..0c0519844c8a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1674,9 +1674,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
-#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
- !(IS_I915G(dev_priv) || \
- IS_I915GM(dev_priv)))
+#define HAS_512_BYTE_Y_TILING(dev_priv) (IS_I915G(dev_priv) || IS_I915GM(dev_priv))
#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 71efccfde122..a716974a8182 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -142,7 +142,7 @@ static void i915_write_fence_reg(struct i915_fence_reg *fence,
GEM_BUG_ON(!is_power_of_2(vma->fence_size));
GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
- if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence)))
+ if (is_y_tiled && !HAS_512_BYTE_Y_TILING(fence_to_i915(fence)))
stride /= 128;
else
stride /= 512;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
