== Series Details == Series: Enable second DBuf slice for ICL and TGL URL : https://patchwork.freedesktop.org/series/70059/ State : warning == Summary == $ dim checkpatch origin/drm-tip f1c5115b93c7 drm/i915: Remove skl_ddl_allocation struct 03280b410f87 drm/i915: Move dbuf slice update to proper place a778a20b2642 drm/i915: Manipulate DBuf slices properly f799788524b4 drm/i915: Correctly map DBUF slices to pipes -:210: CHECK:LINE_SPACING: Please don't use multiple blank lines #210: FILE: drivers/gpu/drm/i915/intel_pm.c:4179: + -:216: CHECK:LINE_SPACING: Please don't use multiple blank lines #216: FILE: drivers/gpu/drm/i915/intel_pm.c:4185: + + -:235: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #235: FILE: drivers/gpu/drm/i915/intel_pm.c:4204: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B), + DBUF_S1_BIT, DBUF_S2_BIT, 0, 0), -:237: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #237: FILE: drivers/gpu/drm/i915/intel_pm.c:4206: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C), + DBUF_S1_BIT, 0, DBUF_S2_BIT, 0), -:239: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #239: FILE: drivers/gpu/drm/i915/intel_pm.c:4208: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C), 0, + DBUF_S1_BIT, DBUF_S2_BIT, 0), -:241: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #241: FILE: drivers/gpu/drm/i915/intel_pm.c:4210: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0) -:260: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #260: FILE: drivers/gpu/drm/i915/intel_pm.c:4229: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B), + DBUF_S2_BIT, DBUF_S1_BIT, 0, 0), -:262: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #262: FILE: drivers/gpu/drm/i915/intel_pm.c:4231: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C), + DBUF_S1_BIT, 0, DBUF_S2_BIT, 0), -:264: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #264: FILE: drivers/gpu/drm/i915/intel_pm.c:4233: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_D), + DBUF_S1_BIT, 0, 0, DBUF_S2_BIT), -:266: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #266: FILE: drivers/gpu/drm/i915/intel_pm.c:4235: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C), + 0, DBUF_S1_BIT, DBUF_S2_BIT, 0), -:268: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #268: FILE: drivers/gpu/drm/i915/intel_pm.c:4237: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_D), + 0, DBUF_S1_BIT, 0, DBUF_S2_BIT), -:270: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #270: FILE: drivers/gpu/drm/i915/intel_pm.c:4239: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D), + 0, 0, DBUF_S1_BIT, DBUF_S2_BIT), -:272: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #272: FILE: drivers/gpu/drm/i915/intel_pm.c:4241: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D), + 0, 0, DBUF_S1_BIT, DBUF_S2_BIT), -:274: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #274: FILE: drivers/gpu/drm/i915/intel_pm.c:4243: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0), -:276: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #276: FILE: drivers/gpu/drm/i915/intel_pm.c:4245: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D), + DBUF_S1_BIT, DBUF_S1_BIT, 0, DBUF_S2_BIT), -:278: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #278: FILE: drivers/gpu/drm/i915/intel_pm.c:4247: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D), + DBUF_S1_BIT, 0, DBUF_S2_BIT, DBUF_S2_BIT), -:280: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #280: FILE: drivers/gpu/drm/i915/intel_pm.c:4249: + DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), + 0, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT) -:291: WARNING:BRACES: braces {} are not necessary for single statement blocks #291: FILE: drivers/gpu/drm/i915/intel_pm.c:4260: + if (dbuf_slices[i].active_pipes == active_pipes) { + return dbuf_slices[i].dbuf_mask[pipe]; + } total: 0 errors, 1 warnings, 17 checks, 319 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
