Found while strolling docs. Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index aa77639..45ffb2c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3342,6 +3342,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) /* Required for CxSR */ dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; + /* WaDisableSVSMUnitClockGating */ I915_WRITE(PCH_3DCGDIS0, MARIUNIT_CLOCK_GATE_DISABLE | SVSMUNIT_CLOCK_GATE_DISABLE); @@ -3353,7 +3354,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) /* * According to the spec the following bits should be set in * order to enable memory self-refresh - * The bit 22/21 of 0x42004 + * The bit 22/21 of 0x42004 (WaDisableDisplayFetchStrideStreching) * The bit 5 of 0x42020 * The bit 15 of 0x45000 */ -- 1.7.10.4
