On Wed, 2019-11-20 at 17:45 +0000, Chris Wilson wrote:
> Quoting Stuart Summers (2019-11-20 17:36:42)
> > In the event a platform does not properly implement reset,
> > do not go through reset flows for engine domains to avoid
> > an unlikely situation where writes are accepted but register
> > values are never cleared, as this can result in GPU wedges
> > in these cases.
> >
> > Signed-off-by: Stuart Summers <stuart.summers@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/gt/intel_reset.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> > b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index 0388f9375366..0454e01e063c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -270,6 +270,12 @@ static int gen6_hw_domain_reset(struct
> > intel_gt *gt, u32 hw_domain_mask)
> > struct intel_uncore *uncore = gt->uncore;
> > int err;
> >
> > + if (!i915_modparams.reset) {
> > + DRM_DEBUG_DRIVER("Skipping 0x%08x engines reset\n",
> > + hw_domain_mask);
> > + return 0;
>
> And it should be -ENODEV. Factor that into your plans :)
Heh, again, might require some rework although I can see the intention
here.
Thanks,
Stuart
> -Chris
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