On 20/11/2019 16:40, Ramalingam C wrote:
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8c441bf10cb1..0a3034e841c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
val = intel_uncore_read(engine->uncore, FF_MODE2);
val &= ~FF_MODE2_TDS_TIMER_MASK;
val |= FF_MODE2_TDS_TIMER_128;
- wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
+ /* At TGL A0 silicon FF_MODE2 reg read is not functional. */
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+ !IS_TGL_REVID(engine->uncore->i915, 0,
+ TGL_REVID_A0));
Why do you need the previous patch and can't just re-add the helper (we
had it at some point) which creates the workaround with wa->read = 0
directly?
wa_write_masked_or__no_verify, or __wa_write_masked_or with read mask
explicitly passed in?
Regards,
Tvrtko
}
static void
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