The gen12 bspec indicates we should disable display interrupts via
DISPLAY_INT_CTL during the display interrupt handler and re-enable them
again at the end. This isn't technically required on gen11, but is
still safe (confirmed internally with hardware architects).
Bspec: 49212
Cc: Aditya Swarup <aditya.swarup@xxxxxxxxx>
Cc: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_irq.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 028cb6239c12..20a06ceae2df 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2477,7 +2477,17 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & GEN11_DISPLAY_IRQ) {
- const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
+ u32 disp_ctl;
+
+ /*
+ * Clear bit 31 to prevent missing any interrupts occurring
+ * back-to-back or during the service routine. Only required
+ * on gen12+, but still safe on gen11 too (assuming we have
+ * the complementary re-enable farther down).
+ */
+ raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0);
+
+ disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
disable_rpm_wakeref_asserts(&i915->runtime_pm);
/*
@@ -2485,7 +2495,12 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
* for the display related bits.
*/
gen8_de_irq_handler(i915, disp_ctl);
+
enable_rpm_wakeref_asserts(&i915->runtime_pm);
+
+ /* Re-enable display interrupt control */
+ raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+ GEN11_DISPLAY_IRQ_ENABLE);
}
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
--
2.21.0
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