== Series Details == Series: drm/i915: Enable second dbuf slice for ICL and TGL (rev4) URL : https://patchwork.freedesktop.org/series/69124/ State : warning == Summary == $ dim checkpatch origin/drm-tip dc5cb9d402db drm/i915: Enable second dbuf slice for ICL and TGL -:48: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #48: - Slices intersection after union is same as final result(Matthew Roper) -:277: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 0) #277: FILE: drivers/gpu/drm/i915/display/intel_display_power.h:311: for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ [...] +int intel_dbuf_max_slices(struct drm_i915_private *dev_priv); -:570: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations #570: FILE: drivers/gpu/drm/i915/intel_pm.c:3952: + u32 pipe_dbuf_slice_mask = \ -:572: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #572: FILE: drivers/gpu/drm/i915/intel_pm.c:3954: + i915_get_allowed_dbuf_mask(dev_priv, + pipe, -:688: CHECK:LINE_SPACING: Please don't use multiple blank lines #688: FILE: drivers/gpu/drm/i915/intel_pm.c:4302: + + -:692: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #692: FILE: drivers/gpu/drm/i915/intel_pm.c:4306: + DRM_DEBUG_KMS("Pipe %d downscale amount %d.%d\n", + crtc->pipe, pipe_downscale.val >> 16, -:714: CHECK:LINE_SPACING: Please don't use multiple blank lines #714: FILE: drivers/gpu/drm/i915/intel_pm.c:4328: + + -:715: CHECK:CAMELCASE: Avoid CamelCase: <DBuf1> #715: FILE: drivers/gpu/drm/i915/intel_pm.c:4329: +#define ICL_PIPE_A_DBUF_SLICES(DBuf1) \ -:723: CHECK:CAMELCASE: Avoid CamelCase: <DBuf2> #723: FILE: drivers/gpu/drm/i915/intel_pm.c:4337: +#define ICL_PIPE_AB_DBUF_SLICES(DBuf1, DBuf2) \ -:735: CHECK:CAMELCASE: Avoid CamelCase: <DBuf3> #735: FILE: drivers/gpu/drm/i915/intel_pm.c:4349: +#define ICL_PIPE_ABC_DBUF_SLICES(DBuf1, DBuf2, DBuf3) \ -:745: CHECK:CAMELCASE: Avoid CamelCase: <DBuf4> #745: FILE: drivers/gpu/drm/i915/intel_pm.c:4359: +#define ICL_PIPE_ABCD_DBUF_SLICES(DBuf1, DBuf2, DBuf3, DBuf4) \ -:854: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #854: FILE: drivers/gpu/drm/i915/intel_pm.c:4468: +u32 i915_get_allowed_dbuf_mask(struct drm_i915_private *dev_priv, + int pipe, u32 active_pipes, total: 0 errors, 3 warnings, 9 checks, 745 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
