On Mon, 11 Nov 2019, Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx> wrote:
> As per the Bspec the port mapping is fixed for mipi dsi
The "tgl" in the patch subject is slightly confusing, because this isn't
new to tgl.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 27 ++++++++++++++++----
> 1 file changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f1328c08f4ad..d4a8617d6185 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10397,21 +10397,38 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
> return transcoder_is_dsi(pipe_config->cpu_transcoder);
> }
>
> -static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> +static enum port
> +intel_transcoder_to_port(struct drm_i915_private *dev_priv,
> + enum transcoder cpu_transcoder)
This is also confusing naming because this is definitely not universal
across platforms.
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_shared_dpll *pll;
> enum port port;
> u32 tmp;
>
> - tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> + /* DSI transcoders have fixed ddi mapping*/
> + if (transcoder_is_dsi(cpu_transcoder)) {
> + port = (cpu_transcoder == TRANSCODER_DSI_A) ? PORT_A : PORT_B;
> + return port;
> + }
I think I'd just add that in the existing haswell_get_ddi_port_state()
without another function.
if (dsi) {
} else {
do the below
>
> + tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (INTEL_GEN(dev_priv) >= 12)
> port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> else
> port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
>
> + return port;
> +}
> +
> +static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_shared_dpll *pll;
> + enum port port;
> + u32 tmp;
> +
> + port = intel_transcoder_to_port(dev_priv, pipe_config->cpu_transcoder);
> +
> if (INTEL_GEN(dev_priv) >= 11)
> icelake_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_CANNONLAKE(dev_priv))
--
Jani Nikula, Intel Open Source Graphics Center
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