On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
> Since CNP it's possible for rawclk to have two different values, 19.2
> and 24 MHz. If the value indicated by SFUSE_STRAP register is different
> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
> mismatch between the rawclk hardware and software states after
> suspend/resume. On previous platforms this used to work by accident,
> because the power on defaults worked just fine.
>
> Update the rawclk also on resume. The natural place to do this is
> intel_modeset_init_hw(), however VLV/CHV need it done before
> intel_power_domains_init_hw(). Split the update accordingly, even if
> that's slighly ugly. This means moving the update later for non-VLV/CHV
> platforms in probe.
>
> Reported-by: Shawn Lee <shawn.c.lee@xxxxxxxxx>
> Cc: Shawn Lee <shawn.c.lee@xxxxxxxxx>
> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++++
> drivers/gpu/drm/i915/i915_drv.c | 3 ---
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e56a75c07043..e31697fdffd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> + /*
> + * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
> + */
> + if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
> intel_update_cdclk(i915);
> intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK");
> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 707ac110e271..999133d1f088 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> + /*
> + * Must happen before power domain init on VLV/CHV, the rest update
> + * rawclk later in intel_modeset_init_hw().
> + */
> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
Can't we just do it here unconditionally? I think this gets called on
the resume path as well.
> +
> if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 21273b516dbe..62906336298a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client;
>
> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
> - intel_update_rawclk(i915);
> -
> intel_power_domains_init_hw(i915, false);
>
> intel_csr_ucode_init(i915);
> --
> 2.20.1
--
Ville Syrjälä
Intel
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