>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville Syrjala
>Sent: Wednesday, October 9, 2019 4:14 PM
>To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>Subject: [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for icl+
>
>From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
>ICL+ again supports alpha blending with 10bpc pixel formats.
>Expose them.
>
>v2: Add all the stuff I missed earlier!
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
>Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++----
>drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++++++++++
> 2 files changed, 25 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1cdcd0ea0564..19a0c8cfb151 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -3031,10 +3031,17 @@ int skl_format_to_fourcc(int format, bool rgb_order,
>bool alpha)
> return DRM_FORMAT_XRGB8888;
> }
> case PLANE_CTL_FORMAT_XRGB_2101010:
>- if (rgb_order)
>- return DRM_FORMAT_XBGR2101010;
>- else
>- return DRM_FORMAT_XRGB2101010;
>+ if (rgb_order) {
>+ if (alpha)
>+ return DRM_FORMAT_ABGR2101010;
>+ else
>+ return DRM_FORMAT_XBGR2101010;
>+ } else {
>+ if (alpha)
>+ return DRM_FORMAT_ARGB2101010;
>+ else
>+ return DRM_FORMAT_XRGB2101010;
>+ }
> case PLANE_CTL_FORMAT_XRGB_16161616F:
> if (rgb_order) {
> if (alpha)
>@@ -4024,8 +4031,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> case DRM_FORMAT_ARGB8888:
> return PLANE_CTL_FORMAT_XRGB_8888;
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ABGR2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010 |
>PLANE_CTL_ORDER_RGBX;
> case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_ARGB2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
>@@ -5617,6 +5626,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_ARGB8888:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
> case DRM_FORMAT_XRGB16161616F:
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 4cd0982dc8a2..df3ca75580d7 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_XRGB16161616F,
> DRM_FORMAT_XBGR16161616F,
> DRM_FORMAT_ARGB16161616F,
>@@ -2315,6 +2321,8 @@ static bool skl_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>@@ -2367,6 +2375,8 @@ static bool gen12_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>--
>2.21.0
>
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