TGL introduced a feature in which we map the main surface to the
auxilliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++++++
drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5cf4eed5add8..0c4d8a895feb 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -741,6 +741,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
if (IS_GEN_RANGE(m->i915, 8, 11))
err_printf(m, "GTT_CACHE_EN: 0x%08x\n", error->gtt_cache);
+ if (IS_TIGERLAKE(m->i915))
+ err_printf(m, "AUX_ERR_DBG: 0x%08x\n", error->aux_err_dbg);
+
for (ee = error->engine; ee; ee = ee->next)
error_print_engine(m, ee, error->epoch);
@@ -1563,6 +1566,11 @@ static void capture_reg_state(struct i915_gpu_state *error)
if (IS_GEN_RANGE(i915, 8, 11))
error->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
+ if (IS_TIGERLAKE(i915)) {
+ error->aux_err_dbg = intel_uncore_read(uncore,
+ GEN12_AUX_ERR_DBG);
+ }
+
/* 4: Everything else */
if (INTEL_GEN(i915) >= 11) {
error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 7f1cd0b1fef7..e0c38b01ed18 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -75,6 +75,7 @@ struct i915_gpu_state {
u32 gab_ctl;
u32 gfx_mode;
u32 gtt_cache;
+ u32 aux_err_dbg; /* tigerlake */
u32 nfence;
u64 fence[I915_MAX_NUM_FENCES];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 855db888516c..62b0b59bf02e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2602,6 +2602,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define FAULT_VA_HIGH_BITS (0xf << 0)
#define FAULT_GTT_SEL (1 << 4)
+#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
+
#define FPGA_DBG _MMIO(0x42300)
#define FPGA_DBG_RM_NOCLAIM (1 << 31)
--
2.24.0.rc0.303.g954a862665
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