On Tue, 2019-10-08 at 14:17 -0700, Matt Roper wrote:
> Gen11+ has more hardware planes than gen9 so we need to test
> additional
> pipe interrupt register bits to recognize any GTT faults that happen
> on
> these extra planes.
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
>
> Bspec: 50335
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 +++-
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index f2371b6083c6..5499450c1524 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2589,7 +2589,9 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
>
> static u32 gen8_de_pipe_fault_mask(struct drm_i915_private
> *dev_priv)
> {
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (INTEL_GEN(dev_priv) >= 11)
> + return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
> + else if (INTEL_GEN(dev_priv) >= 9)
> return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> else
> return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 6d67bd238cfe..24311fee7009 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7373,6 +7373,9 @@ enum {
> #define GEN8_PIPE_VSYNC (1 << 1)
> #define GEN8_PIPE_VBLANK (1 << 0)
> #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
> +#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
> +#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
> +#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
> #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
> #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
> #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
> @@ -7392,6 +7395,11 @@ enum {
> GEN9_PIPE_PLANE3_FAULT | \
> GEN9_PIPE_PLANE2_FAULT | \
> GEN9_PIPE_PLANE1_FAULT)
> +#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
> + (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
> + GEN11_PIPE_PLANE7_FAULT | \
> + GEN11_PIPE_PLANE6_FAULT | \
> + GEN11_PIPE_PLANE5_FAULT)
>
> #define GEN8_DE_PORT_ISR _MMIO(0x44440)
> #define GEN8_DE_PORT_IMR _MMIO(0x44444)
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