On Tue, 2019-10-15 at 22:30 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> To make the logs a bit less confusing let's toss in some
> debug prints to indicate whether the cdclk reprogramming
> is going to happen with a single pipe active or whether we
> need to turn all pipes off for the duration.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3d867963a6d1..6eaebc38ee01 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2343,6 +2343,9 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> return ret;
>
> state->cdclk.pipe = pipe;
> +
> + DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n",
> + pipe_name(pipe));
> } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
> &state->cdclk.actual)) {
> ret = intel_modeset_all_pipes(state);
> @@ -2350,6 +2353,8 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
> return ret;
>
> state->cdclk.pipe = INVALID_PIPE;
> +
> + DRM_DEBUG_KMS("Modeset required for cdclk change\n");
> }
>
> DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz,
> actual %u kHz\n",
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