On Thu, 24 Oct 2019, "Kulkarni, Vandita" <vandita.kulkarni@xxxxxxxxx> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@xxxxxxxxx>
>> Sent: Tuesday, October 22, 2019 7:33 PM
>> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>> Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; Kulkarni, Vandita
>> <vandita.kulkarni@xxxxxxxxx>
>> Subject: [PATCH] drm/i915/bios: add compression parameter block definition
>>
>> Add definition for block 56, the compression parameters.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
>> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 50 +++++++++++++++++++
>> 1 file changed, 50 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> index e3045ced4bfe..7f222196d2d5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> @@ -114,6 +114,7 @@ enum bdb_block_id {
>> BDB_LVDS_POWER = 44,
>> BDB_MIPI_CONFIG = 52,
>> BDB_MIPI_SEQUENCE = 53,
>> + BDB_COMPRESSION_PARAMETERS = 56,
>> BDB_SKIP = 254, /* VBIOS private block, ignore
>> */
>> };
>>
>> @@ -811,4 +812,53 @@ struct bdb_mipi_sequence {
>> u8 data[0]; /* up to 6 variable length blocks */ } __packed;
>>
>> +/*
>> + * Block 56 - Compression Parameters
>> + */
>> +
>> +#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0
>> +#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1
>> +#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2
>> +#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3
>> +
>> +#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /*
>> bits */
>> +#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2)
>> +
>> +struct dsc_compression_parameters_entry {
>> + u8 version_major:4;
>> + u8 version_minor:4;
>> +
>> + u8 rc_buffer_block_size:2;
>> + u8 reserved1:6;
>> +
>> + /*
>> + * Buffer size in bytes:
>> + *
>> + * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
>> + */
>> + u8 rc_buffer_size;
>> + u32 slices_per_line;
>> +
>> + u8 line_buffer_depth:4;
>> + u8 reserved2:4;
>> +
>> + /* Flag Bits 1 */
>> + u8 block_prediction_enable:1;
>> + u8 reserved3:7;
>> +
>> + u8 max_bpp; /* mapping */
>> +
>> + /* Color depth capabilities */
>
> I did not understand the split here, the spec says Bits 7-4 reserved.
Bit 0 *and* bits 7-4 are reserved.
>> + u8 reserved4:1;
>> + u8 support_8bpc:1;
>> + u8 support_10bpc:1;
>> + u8 support_12bpc:1;
>> + u8 reserved5:4;
>
> Do we not need DSC slice height?
Whoops. Posted v2.
Thanks,
Jani.
>
> Regards,
> - Vandita
>> +} __packed;
>> +
>> +struct bdb_compression_parameters {
>> + u16 entry_size;
>> + struct dsc_compression_parameters_entry data[16]; } __packed;
>> +
>> #endif /* _INTEL_VBT_DEFS_H_ */
>> --
>> 2.20.1
>
--
Jani Nikula, Intel Open Source Graphics Center
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