== Series Details == Series: Clear Color Support for TGL Render Decompression (rev7) URL : https://patchwork.freedesktop.org/series/66814/ State : warning == Summary == $ dim checkpatch origin/drm-tip ad3f8ef792a4 drm/framebuffer: Format modifier for Intel Gen-12 render compression 8130c8f3c633 drm/i915: Use intel_tile_height() instead of re-implementing 0513f8dd0e4f drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment aa26ffc536ed drm/i915/tgl: Gen-12 render decompression 3a4093bd96ef drm/i915: Extract framebufer CCS offset checks into a function 130bad161a5f drm/framebuffer: Format modifier for Intel Gen-12 media compression 5f5914ce2a12 drm/fb: Extend format_info member arrays to handle four planes 791ce575f45a Gen-12 display can decompress surfaces compressed by the media engine. -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: compressed buffers. Unlike render decompression, plane 6 and plane 7 do not -:113: WARNING:LONG_LINE: line over 100 characters #113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2713: +intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane) -:120: WARNING:LONG_LINE: line over 100 characters #120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2720: + } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} }; total: 0 errors, 3 warnings, 0 checks, 509 lines checked 471c649e8d20 drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: Gen12 display can decompress surfaces compressed by render engine with Clear Color, add total: 0 errors, 1 warnings, 0 checks, 24 lines checked 4530a97a79f2 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression -:253: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #253: FILE: drivers/gpu/drm/i915/i915_reg.h:6798: +#define PLANE_CC_VAL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe)) total: 0 errors, 0 warnings, 1 checks, 198 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
