Pushed to dinq, thanks for reviews
Manasi
On Fri, Oct 18, 2019 at 10:27:21AM -0700, Manasi Navare wrote:
> In case of tiled displays where different tiles are displayed across
> different ports, we need to synchronize the transcoders involved.
> This patch implements the transcoder port sync feature for
> synchronizing one master transcoder with one or more slave
> transcoders. This is only enbaled in slave transcoder
> and the master transcoder is unaware that it is operating
> in this mode.
> This has been tested with tiled display connected to ICL.
>
> v7:
> * Rebase on Maarten's patches
> v6:
> * Use master_trans +1 and address missing trans_edp case (Ville)
> v5:
> * Add TRANSCODER_D case and MISSING_CASE (Maarten)
> v4:
> Rebase
> v3:
> * Check of DP_MST moved to atomic_check (Maarten)
> v2:
> * Do not use RMW, just write to the register in commit (Jani N)
>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 33 ++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e03132a8c916..aef11087a0fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4405,6 +4405,36 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> }
>
> +static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 trans_ddi_func_ctl2_val;
> + u8 master_select;
> +
> + /*
> + * Configure the master select and enable Transcoder Port Sync for
> + * Slave CRTCs transcoder.
> + */
> + if (crtc_state->master_transcoder == INVALID_TRANSCODER)
> + return;
> +
> + if (crtc_state->master_transcoder == TRANSCODER_EDP)
> + master_select = 0;
> + else
> + master_select = crtc_state->master_transcoder + 1;
> +
> + /* Set the master select bits for Tranascoder Port Sync */
> + trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
> + PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
> + PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
> + /* Enable Transcoder Port Sync */
> + trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
> +
> + I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
> + trans_ddi_func_ctl2_val);
> +}
> +
> static void intel_fdi_normal_train(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -6429,6 +6459,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_set_pipe_timings(pipe_config);
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_enable_trans_port_sync(pipe_config);
> +
> intel_set_pipe_src_size(pipe_config);
>
> if (cpu_transcoder != TRANSCODER_EDP &&
> --
> 2.19.1
>
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