On Tue, 2019-10-15 at 22:05 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The MSA MISC computation now depends on the connector state, and
> we do it from the DDI .pre_enable() hook. All that is fine for
> DP SST but with MST we don't actually pass the connector state
> to the dig port's .pre_enable() hook which leads to an oops.
>
> Need to think more how to solve this in a cleaner fashion, but
> for now let's just add a NULL check to stop the oopsing.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx>
> Cc: Uma Shankar <uma.shankar@xxxxxxxxx>
> Fixes: 0c06fa156006 ("drm/i915/dp: Add support of BT.2020 Colorimetry
> to DP MSA")
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 80f8e2698be0..4c81449ec144 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1794,8 +1794,10 @@ void intel_ddi_set_dp_msa(const struct
> intel_crtc_state *crtc_state,
> * of Color Encoding Format and Content Color Gamut] while
> sending
> * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1
> fields
> * which indicate VSC SDP for the Pixel Encoding/Colorimetry
> Format.
> + *
> + * FIXME MST doesn't pass in the conn_state
> */
> - if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
> + if (conn_state && intel_dp_needs_vsc_sdp(crtc_state,
> conn_state))
> temp |= DP_MSA_MISC_COLOR_VSC_SDP;
>
> I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
Sorry for making of a regression with my commit.
And thank you for fixing oops.
For now this seems good to me for without flow changing of setting of
MSA register.
But as you comments, as a next step we need to think more how to solve
this in a cleaner fashion on SST and MST.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@xxxxxxxxx>
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