On 2019-10-14 at 16:31:21 +0530, Vandita Kulkarni wrote:
> In case of dual link, we get the TE on slave.
> So clear the TE on slave DSI IIR.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 61 +++++++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index bfb2a63504fb..d12efa72943b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2628,6 +2628,61 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> DRM_ERROR("Unexpected DE Misc interrupt\n");
> }
>
> +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
> + u32 iir_value)
> +{
> + enum pipe pipe = INVALID_PIPE;
> + enum port port;
> + enum transcoder dsi_trans;
> + u32 val;
usually we order the declarations based on the length.
> +
> + /*
> + * Incase of dual link, TE comes from DSI_1
> + * this is to check if dual link is enabled
> + */
> + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
> + val &= PORT_SYNC_MODE_ENABLE;
> +
> + /*
> + * if dual link is enabled, then read DSI_0
> + * transcoder registers
> + */
> + port = ((iir_value & ICL_DSI_1) && val) || (iir_value & ICL_DSI_0) ? PORT_A : PORT_B;
wrap it!? beyond 80char?
> + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
> +
> + /* Check if DSI configured in command mode */
> + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
> + val = (val & OP_MODE_MASK) >> 28;
Could we use a macro, like GET_OP_MODE()?
> +
> + if (val) {
> + DRM_ERROR("DSI trancoder not configured in command mode\n");
> + return;
> + }
> +
> + /* Get PIPE for handling VBLANK event */
> + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> + switch (val & TRANS_DDI_EDP_INPUT_MASK) {
> + case TRANS_DDI_EDP_INPUT_A_ON:
> + pipe = PIPE_A;
> + break;
> + case TRANS_DDI_EDP_INPUT_B_ONOFF:
> + pipe = PIPE_B;
> + break;
> + case TRANS_DDI_EDP_INPUT_C_ONOFF:
> + pipe = PIPE_C;
> + break;
> + default:
> + DRM_ERROR("Invalid PIPE\n");
> + }
> +
> + /* clear TE in dsi IIR */
> + port = (iir_value & ICL_DSI_1) ? PORT_B : PORT_A;
> + val = I915_READ(ICL_DSI_INTR_IDENT_REG(port));
> + I915_WRITE((ICL_DSI_INTR_IDENT_REG(port)), val);
extra () around ICL_DSI_INTR_IDENT_REG(port)
> +
> + drm_handle_vblank(&dev_priv->drm, pipe);
> +}
> +
> static irqreturn_t
> gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> {
> @@ -2692,6 +2747,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> found = true;
> }
>
> + if ((INTEL_GEN(dev_priv) >= 11) &&
> + (iir & (ICL_DSI_0 | ICL_DSI_1))) {
alignment.
-Ram
> + gen11_dsi_te_interrupt_handler(dev_priv, iir);
> + found = true;
> + }
> +
> if (!found)
> DRM_ERROR("Unexpected DE Port interrupt\n");
> }
> --
> 2.21.0.5.gaeb582a
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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