On Mon, Oct 14, 2019 at 02:13:31PM +0300, Lisovskiy, Stanislav wrote: > On Fri, 2019-10-11 at 16:49 -0700, James Ausmus wrote: > > > + new_qgv_points_mask |= new_mask_bit; > > > + } > > > + > > > + ret = icl_pcode_restrict_qgv_points(dev_priv, > > > new_qgv_points_mask); > > > + if (ret < 0) > > > + DRM_DEBUG_KMS("Could not restrict required gqv > > > points(%d)\n", ret); > > > > s/gqv/qgv/ > > > > > > Also, if we fail masking off the qgv points that can't support our BW > > req, shouldn't we handle that failure somehow - maybe just disable > > SAGV > > entirely? Better we lose power than have flickering screens... Sounds like dead code to me. My approach is: don't deal with hw/firmware failures until they are proven to exist. The debug msg should be an error so that we get a bug report if this ever happens. -- Ville Syrjälä Intel --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx