On Thu, Oct 10, 2019 at 12:32:39PM -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 5 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index e69fa34528df..f1f41ca8402b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
> bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
> {
> /* PORT E doesn't have HDCP, and PORT F is disabled */
> - return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> + return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> }
>
> static int
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 1cbf3998b361..cf956deb0bdf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -600,6 +600,7 @@ static const struct intel_device_info intel_cherryview_info = {
> .has_logical_ring_preemption = 1, \
> .display.has_csr = 1, \
> .has_gt_uc = 1, \
> + .display.has_hdcp = 1, \
> .display.has_ipc = 1, \
> .ddb_size = 896
>
> @@ -643,6 +644,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> .display.has_ddi = 1, \
> .has_fpga_dbg = 1, \
> .display.has_fbc = 1, \
> + .display.has_hdcp = 1, \
> .display.has_psr = 1, \
> .has_runtime_pm = 1, \
> .display.has_csr = 1, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0fb9030b89f1..b383511b6231 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7643,6 +7643,7 @@ enum {
> #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
>
> #define SKL_DFSM _MMIO(0x51000)
> +#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
Looks correct.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index c01fccfe3cca..5cfa197090e2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -980,6 +980,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> enabled_mask);
>
> info->pipe_mask = enabled_mask;
> +
> + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> + info->display.has_hdcp = 0;
> }
>
> /* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 0cdc2465534b..94165b18ed9b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> func(has_dsb); \
> func(has_fbc); \
> func(has_gmch); \
> + func(has_hdcp); \
> func(has_hotplug); \
> func(has_ipc); \
> func(has_modular_fia); \
> --
> 2.23.0
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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