Quoting Stimson, Dale B (2019-10-04 00:26:24) > > On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote: > > > There's very little variation in non-privileged registers for Tigerlake, > > > so we can mostly inherit the set from gen11. There is no whitelist at > > > present, so we do not need to add any special registers. > > > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > > --- > > > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > > > index df1d655ae..819daafc3 100644 > > > --- a/tests/i915/gem_ctx_isolation.c > > > +++ b/tests/i915/gem_ctx_isolation.c > > > @@ -55,10 +55,11 @@ enum { > > > #define GEN9 (ALL << 9) > > > #define GEN10 (ALL << 10) > > > #define GEN11 (ALL << 11) > > > +#define GEN12 (ALL << 12) > > > > > > #define NOCTX 0 > > > > > > -#define LAST_KNOWN_GEN 11 > > > +#define LAST_KNOWN_GEN 12 > > > > > > static const struct named_register { > > > const char *name; > > > @@ -116,9 +117,9 @@ static const struct named_register { > > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > > > - { "L3_Config", GEN8, RCS0, 0x7034 }, > > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > > > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > > > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > > > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > > > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > > > @@ -852,7 +853,7 @@ igt_main > > > gen = intel_gen(intel_get_drm_devid(fd)); > > > > > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > > > - "GEN not recognized! Test needs to be updated to run."); > > > + "GEN not recognized! Test needs to be updated to run."); > > > igt_skip_on(gen > LAST_KNOWN_GEN); > > On 2019-10-02 14:38:31, Petri Latvala wrote: > > Thanks to this editorial change, we're able to see that this string is > > missing a newline character. > > Your patch looks good (as does Petri's comment). > > I had identified the same registers as in the patch, but had one additional > register. Should it be included? > > + { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked = true }, > > I did some testing on a TGL with your patch. There are two pre-existing > issues, both of which I have encountered before. These are that the S3/S4 test > never wakes up, and errors reported by nonpriv for vcs'2 registers. See below. > > Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require > subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4 > tests for Gen12 until this problem is resolved? No. Fix the problem; it's to do with the interrupts being fubar. > I have been doing some work to address the vcs issue, which I will send > to the mailing list soon. The vcs issue is due to confusion between the > physical engine really being vcs'2, and the kernel presenting the engine to > usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base > expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping" > for ICL and later. Or see the patches to expose the mmio_base. If push comes to shove, it's already given in debugfs for precisely this purpose. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
