From: Michel Thierry <michel.thierry@xxxxxxxxx> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles). FF_MODE2 is part of the register state context, that's why it is implemented here. v2: Rebased on top of the WA refactoring (Oscar) v3: Correctly add to ctx_workarounds_init (Michel) BSpec: 19363 HSDES: 1604555607 Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx> Signed-off-by: Ramalingam C <ramlingam.c@xxxxxxxxx> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++ drivers/gpu/drm/i915/i915_reg.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index ba65e5018978..4049b876492a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -567,9 +567,18 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { + struct drm_i915_private *dev_priv = engine->i915; + u32 val; + /* Wa_1409142259 */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); + + /* Wa_1604555607:tgl */ + val = I915_READ(FF_MODE2); + val &= ~FF_MODE2_TDS_TIMER_MASK; + val |= FF_MODE2_TDS_TIMER_128; + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val); } static void diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 058aa5ca8b73..ff19b8c80b40 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7775,6 +7775,11 @@ enum { #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) +#define FF_MODE2 _MMIO(0x6604) +#define FF_MODE2_TDS_TIMER_SHIFT (16) +#define FF_MODE2_TDS_TIMER_128 (4 << FF_MODE2_TDS_TIMER_SHIFT) +#define FF_MODE2_TDS_TIMER_MASK (0xff << FF_MODE2_TDS_TIMER_SHIFT) + /* PCH */ #define PCH_DISPLAY_BASE 0xc0000u -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx