In prep for newer platforms having more complicated ways to determine
the SAGV block time, extract the setting to a separate function. While
we're at it, update the if ladder to follow the new gen -> old gen order
preference, and warn on any non-specified gen.
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxx>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Signed-off-by: James Ausmus <james.ausmus@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6bed2ed14574..5ad72dcb0faa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3662,6 +3662,23 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
+static int
+intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
+{
+ int sagv_block_time_us = 1000; /* Default to unusable block time */
+
+ if (IS_GEN(dev_priv, 11))
+ sagv_block_time_us = 10;
+ else if (IS_GEN(dev_priv, 10))
+ sagv_block_time_us = 20;
+ else if (IS_GEN(dev_priv, 9))
+ sagv_block_time_us = 30;
+ else
+ MISSING_CASE(INTEL_GEN(dev_priv));
+
+ return sagv_block_time_us;
+}
+
/*
* SAGV dynamically adjusts the system agent voltage and clock frequencies
* depending on power and performance requirements. The display engine access
@@ -3755,12 +3772,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
if (!intel_has_sagv(dev_priv))
return false;
- if (IS_GEN(dev_priv, 9))
- sagv_block_time_us = 30;
- else if (IS_GEN(dev_priv, 10))
- sagv_block_time_us = 20;
- else
- sagv_block_time_us = 10;
+ sagv_block_time_us = intel_get_sagv_block_time_us(dev_priv);
/*
* If there are no active CRTCs, no additional checks need be performed
--
2.22.1
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