On Wed, Sep 25, 2019 at 10:39:32AM -0700, Matt Roper wrote: > If we don't have enough link bandwidth to support the requested mode, we > bail out of intel_dp_compute_link_config() early before the point it > prints the helpful debug messages containing the available/necessary > link bandwidth. Since failures are when these messages are most useful, > let the function proceed with printing those out and then just return > the proper error code at the end. > > Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> Actually, disregard this patch for now; on errors we'd want to be printing the lane counts and such from limits rather than pipe_config which only gets locked in if we find a successful match. This needs a few more tweaks to be useful. Matt > --- > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index e38db7278cf2..4a1f1d0298c2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2083,12 +2083,9 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, > > /* enable compression if the mode doesn't fit available BW */ > DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en); > - if (ret || intel_dp->force_dsc_en) { > + if (ret || intel_dp->force_dsc_en) > ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, > conn_state, &limits); > - if (ret < 0) > - return ret; > - } > > if (pipe_config->dsc_params.compression_enable) { > DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", > @@ -2112,7 +2109,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, > intel_dp_max_data_rate(pipe_config->port_clock, > pipe_config->lane_count)); > } > - return 0; > + return ret; > } > > static int > -- > 2.21.0 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx