Hey, Op 25-09-2019 om 07:53 schreef Matt Roper: > According to the bspec, GLK/CNL have a smaller small joiner RAM buffer > than ICL+. This feels like something that could easily change again on > future platforms, so let's just add a function to return the proper > per-platform buffer size. That may also slightly simplify the upcoming > bigjoiner enabling. > > Since we have to change intel_dp_dsc_get_output_bpp()'s signature to > pass the dev_priv down for the platform check, let's take the > opportunity to also make that function static since it isn't used > outside the intel_dp file. > > Bspec: 20388 > Bspec: 49259 > Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx> > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> Could you hold off on this patch until https://patchwork.freedesktop.org/patch/332828/?series=67203&rev=1 lands? I've moved both functions up a little bit, and makes it easier to land big joiner if I don't have to rebase all. > --- > drivers/gpu/drm/i915/display/intel_dp.c | 29 ++++++++++++++++++------- > drivers/gpu/drm/i915/display/intel_dp.h | 2 -- > 2 files changed, 21 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 829559f97440..e38db7278cf2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -68,9 +68,6 @@ > > #define DP_DPRX_ESI_LEN 14 > > -/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */ > -#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440 > - > /* DP DSC throughput values used for slice count calculations KPixels/s */ > #define DP_DSC_PEAK_PIXEL_RATE 2720000 > #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 > @@ -164,6 +161,10 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, > enum pipe pipe); > static void intel_dp_unset_edid(struct intel_dp *intel_dp); > > +static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, > + int link_clock, u8 lane_count, > + int mode_clock, int mode_hdisplay); > + > /* update sink rates from dpcd */ > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) > { > @@ -541,7 +542,8 @@ intel_dp_mode_valid(struct drm_connector *connector, > true); > } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { > dsc_max_output_bpp = > - intel_dp_dsc_get_output_bpp(max_link_clock, > + intel_dp_dsc_get_output_bpp(dev_priv, > + max_link_clock, > max_lanes, > target_clock, > mode->hdisplay) >> 4; > @@ -1968,7 +1970,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > u8 dsc_dp_slice_count; > > dsc_max_output_bpp = > - intel_dp_dsc_get_output_bpp(pipe_config->port_clock, > + intel_dp_dsc_get_output_bpp(dev_priv, > + pipe_config->port_clock, > pipe_config->lane_count, > adjusted_mode->crtc_clock, > adjusted_mode->crtc_hdisplay); > @@ -4373,8 +4376,18 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) > DP_DPRX_ESI_LEN; > } > > -u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count, > - int mode_clock, int mode_hdisplay) > +static int > +small_joiner_ram_size_bits(struct drm_i915_private *i915) > +{ > + if (INTEL_GEN(i915) >= 11) > + return 7680 * 8; > + else > + return 6144 * 8; > +} > + > +static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, > + int link_clock, u8 lane_count, > + int mode_clock, int mode_hdisplay) > { > u16 bits_per_pixel, max_bpp_small_joiner_ram; > int i; > @@ -4390,7 +4403,7 @@ u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count, > mode_clock; > > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ > - max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / > + max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / > mode_hdisplay; > > /* > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h > index e01d1f89409d..1bcbf44b0b4e 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -103,8 +103,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); > bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); > bool > intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status); > -u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count, > - int mode_clock, int mode_hdisplay); > u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, > int mode_hdisplay); > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
