On Fri, Sep 20, 2019 at 01:42:22PM +0200, Maarten Lankhorst wrote:
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> Also unexport a few functions only used internally in intel_dp.c
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 98 +++++++++++++++++++------
> 1 file changed, 75 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2fceb71f7f70..046e1662d1e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -247,7 +247,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> }
>
> static int
> -intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
> +intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = &intel_dig_port->base;
> @@ -257,6 +257,9 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
>
> int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
>
> + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11)
> + max_dotclk *= 2;
> +
Should we be checking if the specific pipe can do big joiner on the
platform (gen11 vs gen12 differences) and also omitting eDP from
consideration?
> if (type != DP_DS_PORT_TYPE_VGA)
> return max_dotclk;
>
> @@ -505,8 +508,10 @@ u32 intel_dp_fec_to_mode_clock(u32 fec_clock)
> 1000000U);
> }
>
> -static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
> - u32 mode_clock, u32 mode_hdisplay)
> +static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *dev_priv,
> + u32 link_clock, u32 lane_count,
> + u32 mode_clock, u32 mode_hdisplay,
> + bool bigjoiner)
> {
> u32 bits_per_pixel, max_bpp_small_joiner_ram;
> int i;
> @@ -523,6 +528,10 @@ static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
>
> /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay;
> +
> + if (bigjoiner)
> + max_bpp_small_joiner_ram *= 2;
> +
This change is correct, but while confirming in the bspec I noticed that
we may have the wrong DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER value for
gen11+. It indicates 6144 for GLK, CNL, but 7680 for ICL+ (and double
that to 15360 when using big joiner).
Bspec: 20388
Bspec: 49259
> DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
>
> /*
> @@ -531,6 +540,15 @@ static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
> */
> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>
> + if (bigjoiner) {
> + u32 max_bpp_bigjoiner =
> + dev_priv->max_cdclk_freq * 48 /
> + intel_dp_mode_to_fec_clock(mode_clock);
Minor nitpick, but just to match the bspec (PPC * CDCLK * 24 bits /
pixel clock), I'd keep the 2 PPC and 24 bit factors separate here.
> +
> + DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
> + bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> + }
> +
> /* Error out if the max bpp is less than smallest allowed valid bpp */
> if (bits_per_pixel < valid_dsc_bpp[0]) {
> DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
> @@ -553,7 +571,8 @@ static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
> }
>
> static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> - int mode_clock, int mode_hdisplay)
> + int mode_clock, int mode_hdisplay,
> + bool bigjoiner)
> {
> u8 min_slice_count, i;
> int max_slice_width;
> @@ -578,12 +597,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>
> /* Find the closest match to the valid slice count values */
> for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
> - if (valid_dsc_slicecount[i] >
> - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> - false))
> + u8 test_slice_count = bigjoiner ?
> + 2 * valid_dsc_slicecount[i] :
> + valid_dsc_slicecount[i];
> +
> + if (test_slice_count >
> + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
> break;
> - if (min_slice_count <= valid_dsc_slicecount[i])
> - return valid_dsc_slicecount[i];
> +
> + /* big joiner needs small joiner to be enabled */
> + if (bigjoiner && test_slice_count < 4)
> + continue;
> +
> + if (min_slice_count <= test_slice_count)
> + return test_slice_count;
> }
>
> DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
> @@ -603,11 +630,15 @@ intel_dp_mode_valid(struct drm_connector *connector,
> int max_dotclk;
> u16 dsc_max_output_bpp = 0;
> u8 dsc_slice_count = 0;
> + bool dsc = false, bigjoiner = false;
>
> if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return MODE_NO_DBLESCAN;
>
> - max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
> + if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> + return MODE_H_ILLEGAL;
> +
> + max_dotclk = intel_dp_downstream_max_dotclock(intel_dp, false);
>
> if (intel_dp_is_edp(intel_dp) && fixed_mode) {
> if (mode->hdisplay > fixed_mode->hdisplay)
> @@ -619,6 +650,18 @@ intel_dp_mode_valid(struct drm_connector *connector,
> target_clock = fixed_mode->clock;
> }
>
> + if (mode->clock < 10000)
> + return MODE_CLOCK_LOW;
> +
> + if (target_clock > max_dotclk) {
> + max_dotclk = intel_dp_downstream_max_dotclock(intel_dp, true);
> +
> + if (target_clock > max_dotclk)
> + return MODE_CLOCK_HIGH;
> +
> + bigjoiner = true;
> + }
> +
> max_link_clock = intel_dp_max_link_rate(intel_dp);
> max_lanes = intel_dp_max_lane_count(intel_dp);
>
> @@ -639,26 +682,32 @@ intel_dp_mode_valid(struct drm_connector *connector,
> true);
> } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
> dsc_max_output_bpp =
> - intel_dp_dsc_get_output_bpp(max_link_clock,
> + intel_dp_dsc_get_output_bpp(dev_priv,
> + max_link_clock,
> max_lanes,
> target_clock,
> - mode->hdisplay) >> 4;
> + mode->hdisplay,
> + bigjoiner) >> 4;
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> target_clock,
> - mode->hdisplay);
> + mode->hdisplay,
> + bigjoiner);
> }
> +
> + dsc = dsc_max_output_bpp && dsc_slice_count;
> }
>
> - if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
> - target_clock > max_dotclk)
> + /* big joiner configuration needs DSC */
> + if (bigjoiner && !dsc) {
> + DRM_DEBUG_KMS("Link clock needs bigjoiner, but DSC or FEC not available\n");
> return MODE_CLOCK_HIGH;
> + }
Somewhere in this function we probably also need to make sure that the
big joiner is available on the pipe and that we're not using eDP.
Matt
>
> - if (mode->clock < 10000)
> - return MODE_CLOCK_LOW;
> -
> - if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> - return MODE_H_ILLEGAL;
> + if (mode_rate > max_rate && !dsc) {
> + DRM_DEBUG_KMS("Cannot drive without DSC\n");
> + return MODE_CLOCK_HIGH;
> + }
>
> return intel_mode_valid_max_plane_size(dev_priv, mode);
> }
> @@ -2068,14 +2117,17 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> u8 dsc_dp_slice_count;
>
> dsc_max_output_bpp =
> - intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
> + intel_dp_dsc_get_output_bpp(dev_priv,
> + pipe_config->port_clock,
> pipe_config->lane_count,
> adjusted_mode->crtc_clock,
> - adjusted_mode->crtc_hdisplay);
> + adjusted_mode->crtc_hdisplay,
> + false);
> dsc_dp_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> adjusted_mode->crtc_clock,
> - adjusted_mode->crtc_hdisplay);
> + adjusted_mode->crtc_hdisplay,
> + false);
> if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
> DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
> return -EINVAL;
> --
> 2.20.1
>
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--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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