Quoting Mika Kuoppala (2019-09-20 09:14:36)
> Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
>
> > Before we execute a batch, we must first issue any and all TLB
> > invalidations so that batch picks up the new page table entries.
> > Tigerlake's preparser is weakening our post-sync CS_STALL inside the
> > invalidate pipe-control and allowing the loading of the batch buffer
> > before we have setup its page table (and so it loads the wrong page and
> > executes indefinitely).
> >
> > The igt_cs_tlb indicates that this issue can only be observed on rcs,
> > even though the preparser is common to all engines. Alternatively, we
> > could do TLB shootdown via mmio on updating the GTT.
> >
> > By inserting the pre-parser disable inside EMIT_INVALIDATE, we will also
> > accidentally fixup execution that writes into subsequent batches, such
> > as gem_exec_whisper and even relocations performed on the GPU. We should
> > be careful not to allow this disable to become baked into the uABI!
> >
> > Testcase: igt/i915_selftests/live_gtt/igt_cs_tlb
> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 75 ++++++++++++++++++++++++++++-
> > 1 file changed, 74 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index a99166a2d2eb..60b7b163c3d0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -2807,6 +2807,79 @@ static int gen11_emit_flush_render(struct i915_request *request,
> > return 0;
> > }
> >
> > +static u32 preparser_disable(bool state)
> > +{
> > + return MI_ARB_CHECK | 1 << 8 | state;
> > +}
>
> Descriptive enough, so no need to define the mask.
>
> Acked-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
I touched up the note on the impact of disabling the optimisation on the
uABI. This clears up the remaining errors in BAT on rcs0, so just the
vexing multi-engine problem to solve.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
