On Wed, Sep 18, 2019 at 04:34:45PM +0300, Stanislav Lisovskiy wrote: > Added bandwidth calculation algorithm and checks, > similar way as it was done for ICL, some constants > were corrected according to BSpec. BSpec: 53998 > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx> S-o-b should be last tag, so after the version changelog and the Bugzilla tag > > v2: Start using same icl_get_bw_info function to avoid > code duplication. Moved mpagesize to memory info > related structure as it is now dependant on memory type. > Fixed qi.t_bl field assignment. > > v3: Removed mpagesize as unused. Duplicate code and redundant blankline > fixed. > > Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600 This should be Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111600 > --- > drivers/gpu/drm/i915/display/intel_bw.c | 25 ++++++++++++++++++------- > 1 file changed, 18 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index 688858ebe4d0..7080ec73d33c 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -56,7 +56,11 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, > qi->num_channels = (val & 0xf0) >> 4; > qi->num_points = (val & 0xf00) >> 8; > > - qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; > + if (IS_GEN(dev_priv, 11)) { > + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; > + } else if (IS_GEN(dev_priv, 12)) { Preferred style is to have gen checks ordered from newest to oldest > + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16; > + } > > return 0; > } > @@ -132,20 +136,25 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi) > } > > struct intel_sa_info { > - u8 deburst, mpagesize, deprogbwlimit, displayrtids; > + u16 displayrtids; > + u8 deburst, deprogbwlimit; > }; > > static const struct intel_sa_info icl_sa_info = { > .deburst = 8, > - .mpagesize = 16, > .deprogbwlimit = 25, /* GB/s */ > .displayrtids = 128, > }; > > -static int icl_get_bw_info(struct drm_i915_private *dev_priv) > +static const struct intel_sa_info tgl_sa_info = { > + .deburst = 16, > + .deprogbwlimit = 34, /* GB/s */ > + .displayrtids = 256, > +}; > + > +static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) > { > struct intel_qgv_info qi = {}; > - const struct intel_sa_info *sa = &icl_sa_info; > bool is_y_tile = true; /* assume y tile may be used */ > int num_channels; > int deinterleave; > @@ -234,13 +243,15 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, > void intel_bw_init_hw(struct drm_i915_private *dev_priv) > { > if (IS_GEN(dev_priv, 11)) > - icl_get_bw_info(dev_priv); > + icl_get_bw_info(dev_priv, &icl_sa_info); > + else if (IS_GEN(dev_priv, 12)) Same comment here > + icl_get_bw_info(dev_priv, &tgl_sa_info); > } > > static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, > int num_planes) > { > - if (IS_GEN(dev_priv, 11)) > + if (IS_GEN(dev_priv, 11) || IS_GEN(dev_priv, 12)) It would be good to future proof this - if (INTEL_GEN(dev_priv) >= 11) With the above fixed up, Reviewed-by: James Ausmus <james.ausmus@xxxxxxxxx> > /* > * FIXME with SAGV disabled maybe we can assume > * point 1 will always be used? Seems to match > -- > 2.17.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
