SAMPLER_MODE is a context saved/restored register and needs to be loaded
into a context for it to be preserved across a GPU reset -- as has been
done on the previous generations of the same register.
Fixes: 7f0cc34b5349 ("drm/i915/tgl: Implement Wa_1406941453")
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Cc: Stuart Summers <stuart.summers@xxxxxxxxx>
Cc: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 ++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 +---
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 25ae60846398..3419b9d82cfd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -570,6 +570,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_1409142259 */
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+ /* Wa_1406941453:tgl */
+ WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
+ GEN12_SAMPLER_ENABLE_SMALL_PL);
}
static void
@@ -1260,13 +1264,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_GEN(i915, 12)) {
- /* Wa_1406941453:tgl */
- wa_masked_en(wal,
- SAMPLER_MODE,
- SAMPLER_ENABLE_SMALL_PL);
- }
-
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e3a6178aff4..11014c45444e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8936,6 +8936,7 @@ enum {
#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
+#define GEN12_SAMPLER_ENABLE_SMALL_PL REG_BIT(15)
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
@@ -8965,9 +8966,6 @@ enum {
#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
-#define SAMPLER_MODE _MMIO(0xe18c)
-#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
-
#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
#define FLOW_CONTROL_ENABLE (1 << 15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
--
2.23.0
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