On Wed, 2019-09-18 at 16:56 -0700, Matt Roper wrote: > We generally assume future platforms will inherit the behavior of the > most recent platforms, so update our DDC pin mapping defaults to > match > how ICP/TGP behave (i.e., pins starting from GMBUS_PIN_1_BXT for > combo > PHY's and pins starting from GMBUS_PIN_9_TC1_ICP for TC > PHY's). MCC's > non-standard handling of combo PHY C seems like a platform-specific > quirk that is unlikely to be duplicated on future platforms, so > continue > handling it as a special case. > > Without this change, future platforms would default to gen4-style pin > mapping which is almost certainly not what we'll want. > Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > index c500fc9154c8..b9d53eaee80a 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -3029,7 +3029,7 @@ static u8 intel_hdmi_ddc_pin(struct > drm_i915_private *dev_priv, > > if (HAS_PCH_MCC(dev_priv)) > ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); > - else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv)) > + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > ddc_pin = icl_port_to_ddc_pin(dev_priv, port); > else if (HAS_PCH_CNP(dev_priv)) > ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
