During S0ix/S3 suspend stress test on Cometlake chromebook,
after few iterations we are seeing failure wrt PSR link CRC
Error and stress test stops. This S0ix test is failing only
when there is a CRC mismatch. In case of CRC mismatch, panel
generates IRQ_HD and whenever there is CRC mismatch, we are
disabling PSR2 in driver.
By not disabling PSR2 in driver and only by writing 1 to clear
sticky bit 0 in DPCD 0x2006 in panel,issue goes away.
Completed 2500 S0ix/S3 test cycles on multiple CML chromebooks.
As per EDP spec for CRC mismatch, nothing has been mentioned
explicitly for Source device, only by writing 1 to clear
sticky bit 0 in DPCD 0x2006 in sink is mentioned.
Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b3c7eef53bf3..502e29dbbea9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1325,15 +1325,11 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
if (val & DP_PSR_LINK_CRC_ERROR)
- DRM_ERROR("PSR Link CRC error, disabling PSR\n");
+ DRM_DEBUG_KMS("PSR Link CRC error, clearing PSR error status DPCD\n");
if (val & ~errors)
DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
val & ~errors);
- if (val & errors) {
- intel_psr_disable_locked(intel_dp);
- psr->sink_not_reliable = true;
- }
/* clear status register */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
exit:
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
