Quoting Arkadiusz Hiler (2019-09-12 13:54:18) > Without it we get: > Unclaimed read from register 0x1e1110 > WARNING: CPU: 2 PID: 1029 at drivers/gpu/drm/i915/intel_uncore.c:1101 __unclaimed_reg_debug+0x40/0x50 [i915] > Call Trace: > fwtable_read32+0x233/0x300 [i915] > i915_interrupt_info+0xa73/0xd60 [i915] > seq_read+0xdb/0x3c0 > full_proxy_read+0x51/0x80 > vfs_read+0x9e/0x160 > ksys_read+0x8f/0xe0 > do_syscall_64+0x55/0x1c0 > entry_SYSCALL_64_after_hwframe+0x49/0xbe > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109824 > Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index e5835337f022..29f3436167a2 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -534,6 +534,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > > gen8_display_interrupt_info(m); > } else if (IS_VALLEYVIEW(dev_priv)) { > + intel_wakeref_t pref; checkpath will complain about missing newline between variable block and code. > seq_printf(m, "Display IER:\t%08x\n", > I915_READ(VLV_IER)); > seq_printf(m, "Display IIR:\t%08x\n", > @@ -544,7 +545,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > I915_READ(VLV_IMR)); > for_each_pipe(dev_priv, pipe) { > enum intel_display_power_domain power_domain; > - intel_wakeref_t pref; > > power_domain = POWER_DOMAIN_PIPE(pipe); > pref = intel_display_power_get_if_enabled(dev_priv, > @@ -578,12 +578,14 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > seq_printf(m, "PM IMR:\t\t%08x\n", > I915_READ(GEN6_PMIMR)); > > + pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); > seq_printf(m, "Port hotplug:\t%08x\n", > I915_READ(PORT_HOTPLUG_EN)); > seq_printf(m, "DPFLIPSTAT:\t%08x\n", > I915_READ(VLV_DPFLIPSTAT)); > seq_printf(m, "DPINVGTT:\t%08x\n", > I915_READ(DPINVGTT)); > + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref); Seems reasonable explanation. Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Hopefully, that is enough. If not, we need to ask Imre what the correct power domain should be :) -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
