On Wed, Sep 11, 2019 at 04:31:29PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Reuse the same .modeset_calc_cdclk() function for all bxt+.
>
> The only difference in between the cnl/icl and the bxt variants
> is the call to cnl_compute_min_voltage_level(). We can do that call
> just fine on older platforms since they leave min_voltage_level[]
> zeroed. Let's rename the function to bxt_compute_min_voltage_level()
> just so it stays consistent with the rest of the naming scheme.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +++++-----------------
> 1 file changed, 9 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f5a99eb77efa..b8b3814ba116 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2017,6 +2017,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> }
>
> /*
> + * Account for port clock min voltage level requirements.
> + * This only really does something on CNL+ but can be
> + * called on earlier platforms as well.
> + *
> * Note that this functions assumes that 0 is
> * the lowest voltage value, and higher values
> * correspond to increasingly higher voltages.
> @@ -2025,7 +2029,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> * future platforms this code will need to be
> * adjusted.
> */
> -static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
> +static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> @@ -2195,43 +2199,11 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
>
> - state->cdclk.logical.vco = vco;
> - state->cdclk.logical.cdclk = cdclk;
> - state->cdclk.logical.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk);
> -
> - if (!state->active_pipes) {
> - cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> - state->cdclk.actual.vco = vco;
> - state->cdclk.actual.cdclk = cdclk;
> - state->cdclk.actual.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk);
> - } else {
> - state->cdclk.actual = state->cdclk.logical;
> - }
> -
> - return 0;
> -}
> -
> -static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - int min_cdclk, cdclk, vco;
> -
> - min_cdclk = intel_compute_min_cdclk(state);
> - if (min_cdclk < 0)
> - return min_cdclk;
> -
> - cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
> - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
> -
> state->cdclk.logical.vco = vco;
> state->cdclk.logical.cdclk = cdclk;
> state->cdclk.logical.voltage_level =
> max(dev_priv->display.calc_voltage_level(cdclk),
> - cnl_compute_min_voltage_level(state));
> + bxt_compute_min_voltage_level(state));
>
> if (!state->active_pipes) {
> cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> @@ -2466,17 +2438,17 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
> if (IS_ELKHARTLAKE(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
> dev_priv->cdclk.table = cnl_cdclk_table;
> } else if (IS_GEN9_LP(dev_priv)) {
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
