Quoting Kenneth Graunke (2019-09-10 23:42:26) > This allows userspace to use "legacy" mode for push constants, where > they are committed at 3DPRIMITIVE or flush time, rather than being > committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11 > both use the "legacy" behavior - only Gen9 works in the "new" way. > > Conflating push constants with binding tables is painful for userspace, > we would like to be able to avoid doing so. > > Cc: stable@xxxxxxxxxxxxxxx > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 243d3f77be13..41d0f786e06d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1062,6 +1062,9 @@ static void gen9_whitelist_build(struct i915_wa_list *w) > > /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ > whitelist_reg(w, GEN8_HDC_CHICKEN1); > + > + /* WaSendPushConstantsFromMMIO:skl,bxt */ > + whitelist_reg(w, COMMON_SLICE_CHICKEN2); A couple bits in there look like they could do with a validation pass to make sure they don't kill the machine when incorrectly set. However, we can raise the bar tomorrow, for now this doesn't look any worse than any other potential bad bit. Passed our sanity checks that this is ordinarily a privileged register (i.e. whitelisting is required) and that it is context saved, so include a s-o-b and Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> (s-o-b required!) -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
